In the field of modern VLSI (Very Large Scale Integration) integrated circuit (IC) devices, Metal Oxide Semiconductor Field Effect Transistor (MOSFET) devices often have rarely switching periods such as during low power modes, or are simply rarely switching devices, for example within control logic etc. During such periods of non- (or infrequent) switching, a MOSFET device is subjected to a constant bias voltage, which can result in the PMOSFET or NMOSFET device experiencing respectively Negative Bias Temperature Instability (NBTI) or Positive Bias Temperature Instability (PBTI) stress. N/PBTI stress can cause key reliability issues in MOSFET devices, and manifests as an increase in the threshold voltage (Vth) and consequently a decrease in the drain current and transconductance of the MOSFET device, which results in performance degradation of the MOSFET device.
In order to compensate for such performance degradation of MOSFET devices caused by NBTI/PBTI stress, it is conventional to provide additional margins within the delay of signal paths throughout the IC device, for example up to 10%. However, a problem with this conventional approach is that it introduces extra costs in terms of additional area, power and design effort across the entire IC device, including for those parts of the IC device that do not suffer from significant NBTI/PBTI stress, and thus which do not require such generous additional margins.